HiPChips Chiplet Workshop @ ISCA 2022 – co-located at the ISCA Conference- call for papers.
· Posted by Dharmesh Jani - OCP Incubation Committee Co-Chair (Meta)
The 1st International workshop on the High Performance Chiplet and Interconnect Architectures (code named “HipChips”), organized by the OCP ODSA working group, is a new workshop targeting research between academia and industry. This workshop helps researchers share the latest progress on chiplet-powered architectures for data-intensive applications and ML/HPC-motivated chiplet designs and helps promote the open chiplet standards to foster collaborations on further development of the chiplet ecosystem. The call for papers to present at the workshop is officially open.
TheInternational Symposium on Computer Architecture(ISCA) conference is the premier forum for new ideas and research results in computer architecture. In June of 2022, the 49thedition of ISCA will be held in New York City, New York, USA.
TheOpen Compute Project Foundation (OCP) was initiated in 2011 with amission to apply the
benefits ofopen source and open collaborationto hardware and rapidly increase the pace of
innovation in, near and around the data center’snetworking equipment, general purpose and
GPU servers,storage devices and appliances, and scalable rack designs.OCP’s collaboration
model is beingapplied beyond the data center, helping to advance the telecom industry & EDGE infrastructure. Learn more at www.opencompute.org.
OCP’s Open Domain Specific Architecture (ODSA) Project Community’s mission is to offer a new design option to heterogeneous integrated systems. ODSA Community is proposing a low-cost, high performance open-accelerator architecture to address the full stack of requirements to develop a DSA.
Conference dates: June 18th to 22nd, 2022
- Call for workshop papers: Feb 15th
- Submission deadline: March 31st
- Submission acceptance: April 15th
- Agenda Publication: May 1st
- Final Papers presentations due by:May 13th
- Content review and final feedback: May 26th
- Workshop date:June 19th
Learn more about the workshop and learn how to submit your paper for a speaking spot here:https://www.opencompute.org/summit/ocp-at-the-isca-conference
Submit your paper by email to: ISCAchiplets@opencompute.org
Background
Machine learning (ML), high performance computing (HPC), and the convergence of both are
becoming the major driving force to define future computer architectures in both data center
and edge. As performance requirements of workloads have catapulted, heterogeneous
computing with domain-specific accelerators (DSA) is deemed as a new computing paradigm to
meet the computation demand in the post-Moore era.
While an accelerator architecture is still evolving to continuously integrate more components to
boost its computing horsepower, the increasing cost of silicon results in the rise of chiplet
architectures.
As a promising alternative to advance a chip design, chiplets take advantages of the recent
development of packaging technologies to reduce the complexity of traditional monolithic
system-on-a-chip (SoC) design by improving system-level interconnection density and reducing
power consumption via mix-and-matching existing or new components and integrating them
into a single package. The modularized approach presumably can shorten the development
time and improve yield to lower the manufacturing costs. However, one of the biggest
challenges industry currently faces is lack of standards and tools to allow different pieces of
silicon across vendors to be tied together and work seamlessly through a common interface.
At the same time, as individual devices continue to shrink and more heterogeneous chiplets are
integrated, innovations on chiplet-based computing architectures will be required. Though
communication between chiplets is typically slower than on-chip communication, distances are
shorter and there might be more conduits for inter-chip signals. Thus, collectively inter-chiplet
communication may be faster with less energy consumption. So how to distribute data among
chiplets and optimize data movement for efficient spatial parallel processing is another key to
success.
ODSA"s goal is to create an open chiplet marketplace that allows systems in packages to be built
from building blocks from multiple vendors with speed and simplicity to enable shipping new
solutions faster. To achieve this, ODSA strategy is centered on following three core areas:
- Area 1: Enable open die to die interfaces to reduce barrier for interoperation
- Area 2: Create reference designs as starting points for allowing technology development
- Area 3: Define business reference workflows for enabling reusable, open practices
Submission format for the workshop talks:
We request all submitters to follow the following format for their workshop talk submissions.
Title of Talk
Presenters and affiliations (name, company name, title, email, phone, location)
Categories:
- Chiplet-based accelerator level parallelism (ALP)
- Chiplet architecture for large scale system design
- Physical and logical inter-die interface design for heterogeneous architectures
- Coherent and non-coherent data sharing protocols via fast chiplet interconnection
- Chiplet architectures for in-memory computing and other emerging technologies
- ODSA-based 3D architecture for efficient ML acceleration
- Chiplet-based secure computing
- Power evaluation and performance modeling of chiplet architecture
- Software optimization framework with fast inter-chiplet network
- Chiplet topology aware ML optimizations
- Scheduling for massive heterogeneous chiplet-based processors
- Electro-optical Chiplet Interconnects
- Bootstrapping Chiplet ecosystems
- Other
- Abstract summary (1-2 pages):
- Include relevance to HipChips focus
- Brief abstract or the summary of the talk. What is the talk about?
- No proprietary information or confidential info
- Technology centric - not a marketing/product pitch
Interested in speaking?
Submit an Abstract
